Microelectronic assemblies having conductive structures with different thicknesses

ABSTRACT

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of (and claims the benefit andpriority under 35 U.S.C. 120 of) U.S. application Ser. No. 16/268,813,filed Feb. 6, 2019, entitled “MICROELECTRONIC ASSEMBLIES HAVINGCONDUCTIVE STRUCTURES WITH DIFFERENT THICKNESSES,” the disclosure ofwhich is considered part of, and is incorporated by reference in, thedisclosure of this application.

BACKGROUND

Integrated circuit devices are conventionally coupled to a packagesubstrate for mechanical stability and to facilitate connection to othercomponents via conductive pathways in the package substrate, such ascircuit boards. The conductive pathways may include signal traces forthe routing of signals.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detaileddescription in conjunction with the accompanying drawings. To facilitatethis description, like reference numerals designate like structuralelements. Embodiments are illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings.

FIG. 1A is a side, cross-sectional view of an example microelectronicassembly, in accordance with various embodiments.

FIG. 1B is a side, cross-sectional, magnified view of a portion of thesubstrate of FIG. 1A, in accordance with various embodiments.

FIGS. 2A-2F are side, cross-sectional views of various stages in anexample process for manufacturing a microelectronic assembly, inaccordance with various embodiments.

FIG. 3 is a process flow diagram of an example method of forming amicroelectronic assembly, in accordance with various embodiments.

FIG. 4 is a side, cross-sectional view of an example microelectronicassembly, in accordance with various embodiments.

FIG. 5 is a block diagram of an example electrical device that mayinclude a microelectronic assembly, in accordance with any of theembodiments disclosed herein.

DETAILED DESCRIPTION

Microelectronic assemblies that include a substrate having two or moreconductive traces with different thicknesses thereon and related devicesand methods are disclosed herein. For example, in some embodiments, amicroelectronic assembly may include a substrate having a surface,wherein the substrate includes an electroless catalyst and aphoto-imageable dielectric; a first conductive trace having a firstthickness on the surface of the substrate; and a second conductive tracehaving a second thickness on the surface of the substrate, wherein thesecond thickness is different from the first thickness. In someembodiments, a method of manufacturing a microelectronic assembly mayinclude depositing an electroless catalyst-doped photo-imageabledielectric (PID) on a substrate; laser drilling the electrolesscatalyst-doped PID to form a first opening having a first thickness anda second opening having a second thickness, wherein the first thicknessis greater than the second thickness; and depositing a conductivematerial in the first opening to form a first conductive trace havingthe first thickness and in the second opening to form a secondconductive trace having the second thickness.

Communicating large numbers of signals in an integrated circuit (IC)package is challenging due to the increasingly small size of IC dies,thermal constraints, z-height constraints, form factor constraints,performance constraints, and power delivery constraints, among others.In some embodiments, it may be desirable for traces to have differentcross-sectional areas and/or different thicknesses (e.g., a first tracehaving a greater cross-sectional area (i.e., x-y direction) and/or agreater thickness (i.e., z-height) as compared to a second trace). Agreater cross-sectional area and/or a greater thickness may provide forreduced direct current resistance (DCR) and increased efficiency. Theincreased efficiency may have benefits, such as enabling a longerbattery life or requiring less power. As used herein, a trace may referto a conductive pathway that is to carry data signals to or from acomponent coupled with the trace. For example, a trace may carry datasignals between various processors, or between a processor and a memory.

Forming traces having different thicknesses typically requires twolithography steps, which is likely to cause misalignment betweenlithography steps and may require larger traces to compensate for themisalignment and/or may require larger input/output (I/O) rules. Largertraces and constrained routing space may decrease IC device performancedue to mismatched impedances for different traces. Further, formingtraces having different thicknesses using two lithography steps usuallyresults in non-rectilinear traces (e.g., traces having surfaces that arenot straight or linear), or traces having a cross-section that isnon-rectangular to offset the misalignment error between steps. Forexample, a trace may have a larger cross-section for a first conductivematerial deposition as compared to a second conductive materialdeposition, or a trace may have a curved surface resulting from a secondconductive material deposition having a larger cross-section and/orrounded or domed top surface as compared with a first conductivematerial deposition, where the second conductive material depositioncompletely covers the first material deposition. Various ones of themicroelectronic assemblies disclosed herein may exhibit increasedefficiency, better power delivery, increased efficiency, and increasedbattery life relative to conventional approaches. The microelectronicassemblies disclosed herein may be particularly advantageous forhigh-performance computing, and multiple chip IC packages.

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof wherein like numeralsdesignate like parts throughout, and in which is shown, by way ofillustration, embodiments that may be practiced. It is to be understoodthat other embodiments may be utilized, and structural or logicalchanges may be made, without departing from the scope of the presentdisclosure. Therefore, the following detailed description is not to betaken in a limiting sense.

Various operations may be described as multiple discrete actions oroperations in turn, in a manner that is most helpful in understandingthe claimed subject matter. However, the order of description should notbe construed as to imply that these operations are necessarily orderdependent. In particular, these operations may not be performed in theorder of presentation. Operations described may be performed in adifferent order from the described embodiment. Various additionaloperations may be performed, and/or described operations may be omittedin additional embodiments.

For the purposes of the present disclosure, the phrase “A and/or B”means (A), (B), or (A and B). For the purposes of the presentdisclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B),(A and C), (B and C), or (A, B, and C). The drawings are not necessarilyto scale. Although many of the drawings illustrate rectilinearstructures with flat walls and right-angle corners, this is simply forease of illustration, and actual devices made using these techniqueswill exhibit rounded corners, surface roughness, and other features.

The description uses the phrases “in an embodiment” or “in embodiments,”which may each refer to one or more of the same or differentembodiments. Furthermore, the terms “comprising,” “including,” “having,”and the like, as used with respect to embodiments of the presentdisclosure, are synonymous. As used herein, a “package” and an “ICpackage” are synonymous, as are a “die” and an “IC die.” The terms “top”and “bottom” may be used herein to explain various features of thedrawings, but these terms are simply for ease of discussion, and do notimply a desired or required orientation. As used herein, the term“insulating” may mean “electrically insulating,” unless otherwisespecified.

When used to describe a range of dimensions, the phrase “between X andY” represents a range that includes X and Y. For convenience, the phrase“FIG. 1 ” may be used to refer to the collection of drawings of FIGS.1A-1B, the phrase “FIG. 2 ” may be used to refer to the collection ofdrawings of FIGS. 2A-2F, etc. Although certain elements may be referredto in the singular herein, such elements may include multiplesub-elements. For example, “an insulating material” may include one ormore insulating materials.

As used herein, “conductive pathways” may include conductive traces,pads, vias, and through-holes, and other conductive structures thatelectrically couple an IC package component to another IC packagecomponent or to another component external to the IC package. As usedherein, the terms “trace” and “line” may be used interchangeably and mayrefer to an interconnect in a conductive layer. As used herein,“conductive structures,” “conductive features,” and “conductiveelements” may be used interchangeably and may refer to a trace, a line,a plane, a pad, a via, or another conductive component. The terms“trace,” “routing trace,” and “signal trace” may be used interchangeablyherein.

FIG. 1A is a side, cross-sectional view of a microelectronic assembly100A, in accordance with various embodiments. The microelectronicassembly 100A may include a package substrate 102 having a plurality ofconductive layers that alternate with a plurality of dielectric layers.In particular, the package substrate 102 may include a dielectric layerhaving an electroless catalyst-doped PID material 103. The packagesubstrate 102 may further include a conductive layer in the electrolesscatalyst-doped PID material 103 having a first conductive feature 118with a first thickness (T1) and a second conductive feature 128 with asecond thickness (T2), where the first thickness (T1) is different fromthe second thickness (T2). For example, as shown in FIG. 1A, the firstthickness is greater than the second thickness. In some embodiments, thefirst thickness may be less than the second thickness. In particular,the first conductive feature 118 and the second conductive feature 128may be in (e.g., surrounded by) the electroless catalyst-doped PIDmaterial 103. The electroless catalyst-doped PID material 103 may beselectively activated in laser-ablated areas and may be removed to formopenings. The laser may reduce the catalyst to a catalytically activestate to enable selective laser-patterning in the electrolesscatalyst-doped PID for electroless plating.

The electroless catalyst-doped PID material 103 may include any suitableelectroless catalyst, including, for example, palladium, gold, silver,ruthenium, cobalt, copper, nickel, silicon carbide, silicon nitride,barium titanate, lead titanate, tantalum nitride, aluminum oxide, andaluminum nitride. In some embodiments, the electroless catalyst-dopedPID material 103 may include more than one electroless catalyst. In someembodiments, an electroless catalyst-doped PID may include anelectroless catalyst of up to 10 weight percent. In some embodiments,the amount of electroless may depend on a desired plating rate. Forexample, a PID including palladium as a dopant catalyst may include upto 1 weight percent of palladium and a PID including barium titanate asa dopant catalyst may include up to 10 weight percent of bariumtitanate. In some embodiments, an electroless catalyst-doped PID mayinclude up to 5 weight percent of palladium. The electroless catalystdopant may be detected using any suitable process, including x-rayphotoelectron spectroscopy (XPS), energy-dispersive spectroscopy (EDS),or Fourier-transform infrared spectroscopy (FTIR), among others.

The electroless catalyst-doped PID material 103 may include any suitablephoto-imageable dielectric. As used herein, the term “photo-imageablematerial” and “photodefinable material” may be used interchangeably.More generally, any of the microelectronic assemblies 100 disclosedherein may include a photo-imageable material in which a recess or anopening may be defined, or whose manufacture includes the formation of arecess or opening in a photo-imageable material (e.g., as discussedbelow with reference to FIG. 2 ), as disclosed herein. As used herein, a“photo-imageable material” refers to a material that includesphotocatalytic components that cross-link or render the material solublewhen exposed to appropriate illumination. Some photodefinable materialsmay have a negative tone (i.e., exposure to illumination causes thematerial to cure in a manner that resists etching during development),and other photodefinable materials may have a positive tone (i.e.,exposure to illumination causes the material to cure in a manner thatenhances etching during development). For example, in some embodiments,the electroless catalyst-doped PID material 103 may include a positivetone PID material (e.g., a diazobenzoquionone with an acetyl backbonepolymer), and in other embodiments, the electroless catalyst-doped PIDmaterial 103 may include a negative-tone PID (e.g., an acrylate with anester backbone polymer). Some photodefinable materials may be solderresist materials; such materials may come in contact with solder duringa reflow process (e.g., when forming interconnects 138). In someembodiments, a photodefinable material that is a solder resist mayinclude barium and sulfur (e.g., in the form of barium sulfate). In someembodiments, a photodefinable material that is a solder resist mayinclude a silica filler in the amount of 70 percent to 90 percent byweight. Some photodefinable materials may be photo-imageable dielectric(PID) materials, such as epoxides that include photocatalyticcomponents. In some embodiments, a photodefinable material that is aphoto-imageable dielectric may include a silica filler in the amount of20 percent to 30 percent by weight. Some photodefinable materials may bebuild-up materials, such as a build-up film. In some embodiments, aphotodefinable material that is a build-up material may include a silicafiller in the amount of 70 percent to 80 percent by weight. Otherphotodefinable materials may be used as appropriate.

The plurality of dielectric layers in the package substrate 102 mayinclude any suitable dielectric material, for example, epoxy-basedmaterials/films, ceramic/silica filled epoxide films, polyimide films,filled polyimide films, other organic materials, and other inorganicdielectric materials known from semiconductor processing, as well assilicon dioxide (SiO₂), carbon doped oxide (CDO), silicon nitride,organic polymers such as perfluorocyclobutane orpolytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicatessuch as silsesquioxane, siloxane, or organosilicate glass (OSG). Anindividual dielectric layer may include a single layer or may includemultiple layers.

The plurality of dielectric layers of the package substrate 102,including the electroless catalyst-doped PID material 103, may be formedusing any suitable process, including, for example, chemical vapordeposition (CVD), film lamination, slit coating and curing, atomic layerdeposition (ALD), or spin-on process, among others, and with anysuitable material. In some embodiments, a PID may be deposited bylamination and patterned by exposure to light.

The package substrate 102 may include one or more conductive pathwaysthrough the dielectric material (e.g., conductive pathways may include aconductive trace 117 and/or a conductive via 119, as shown in FIG. 1A).The conductive pathways may be formed using any suitable conductivematerial or materials, such as copper, silver, nickel, gold, aluminum,or other metals or alloys, for example. The conductive pathways may beformed using any suitable technique, such as electroplating. Theconductive pathways in the package substrate 102 may be bordered byliner materials, such as adhesion liners and/or barrier liners, assuitable. An individual conductive layer may include a single layer ormay include multiple layers; for example, a conductive layer may includea seed layer and a patterned trace layer. In some embodiments, aconductive layer may be a patterned trace layer. In some embodiments, aconductive layer may be a continuous layer. Although FIG. 1A illustratesa specific number and arrangement of conductive pathways in the packagesubstrate 102, these are simply illustrative, and any suitable numberand arrangement may be used.

The package substrate 102 may be any suitable substrate, and, in someembodiments, may not be a package substrate. In some embodiments, thesubstrate may be an organic or inorganic interposer, redistributionlayer (RDL), or a standard build-up layer. The package substrate 102 maybe a cored or coreless substrate of a semiconductor package. The packagesubstrate 102 may be glass, an organic package substrate, an inorganicpackage substrate, or a combination of organic and inorganic materials.

Microelectronic assembly 100A may include a die 114. The die 114 may becoupled to the package substrate 102 by first-level interconnects (FLI)138 at a top surface 170-2 of the package substrate 102. In particular,the package substrate 102 may include conductive contacts 140 at its topsurface 170-2, the die 114 may include conductive contacts 136 at itsbottom surface, and the FLI 138 may electrically and mechanically couplethe conductive contacts 136 and the conductive contacts 140. The FLI 138illustrated in FIG. 1A are solder balls or solder bumps (e.g., for aball grid array arrangement), but any suitable FLI 138 may be used(e.g., pins in a pin grid array arrangement or lands in a land gridarray arrangement).

The die 114 may include a semiconductor layer with active devicespatterned on it (e.g., transistors, diodes, etc.), an insulatingmaterial (e.g., a dielectric material formed in multiple layers, orsemiconductor material, as known in the art), and multiple conductivepathways formed through the insulating material. In some embodiments,the insulating material of a die 114 may include a dielectric material,such as silicon dioxide, silicon nitride, BT resin, polyimide materials,glass reinforced epoxy matrix materials, or low-k and ultra low-kdielectric (e.g., carbon doped dielectrics, fluorine-doped dielectrics,porous dielectrics, and organic polymeric dielectrics). For example, thedie 114 may include a dielectric build-up film, such as Ajinomotobuild-up film (ABF). In some embodiments, the insulating material of die114 may be a semiconductor material, such as silicon, germanium, or aIII-V material. In some embodiments, the die 114 may include silicon.The conductive pathways in die 114 may include conductive traces and/orconductive vias, and may connect any of the conductive contacts in thedie 114 in any suitable manner (e.g., connecting multiple conductivecontacts on a same surface of the die 114).

In some embodiments, the area between the die 114 and the packagesubstrate 102 may be filled with underfill (not shown), which may be amold compound or any other suitable material to fill the gap between thedie 114 and the package substrate 102. Underfill may be applied usingany suitable technique, such as transfer mold, capillary underfill, orepoxy flux as part of the thermocompression bonding (TCB) process. Insome embodiments, the underfill may extend beyond the area defined bythe die 114.

Although FIG. 1A depicts a single die 114, the microelectronic assembly100A may have any suitable number of dies. In some embodiments, the die114 may be an active or passive die that may include input/outputcircuitry, high bandwidth memory, or enhanced dynamic random accessmemory (EDRAM). For example, the die 114 may include a processor (e.g.,including transistors, arithmetic logic units, and other components)that may include a central processing unit (CPU), a graphics processingunit (GPU), or both. The processor may also include application-specificintegrated circuits (ASIC). In some embodiments, microelectronicassemblies disclosed herein may include a plurality of dies coupled tothe package substrate 102 or coupled to another die in apackage-on-package (PoP) configuration. In some embodiments, themicroelectronic assembly 100A may serve as a system-in-package (SiP) inwhich multiple dies having different functionality are included. In suchembodiments, the microelectronic assembly may be referred to as an SiP.

The microelectronic assembly 100A of FIG. 1A may also include a circuitboard 134. The package substrate 102 may be coupled to the circuit board134 by second-level interconnects (SLI) 137 at a bottom surface 170-1 ofthe package substrate 102. In particular, the package substrate 102 mayinclude conductive contacts 139 at its bottom surface 170-1, and thecircuit board 134 may include conductive contacts 135 at its topsurface; the SLI 137 may electrically and mechanically couple theconductive contacts 135 and the conductive contacts 139. The SLI 137illustrated in FIG. 1A are solder balls (e.g., for a ball grid arrayarrangement), but any suitable SLI 137 may be used (e.g., pins in a pingrid array arrangement or lands in a land grid array arrangement). Thecircuit board 134 may be a motherboard, for example, and may have othercomponents attached to it (not shown). The circuit board 134 may includeconductive pathways and other conductive contacts (not shown) forrouting power, ground, and signals through the circuit board 134, asknown in the art. In some embodiments, the SLI 137 may not couple thepackage substrate 102 to a circuit board 134, but may instead couple thepackage substrate 102 to another IC package, an interposer, or any othersuitable component.

A number of elements are illustrated in FIG. 1A, but a number of theseelements may not be present in microelectronic assemblies disclosedherein. For example, in various embodiments, the SLI 137, and/or thecircuit board 134 may not be included. Further, FIG. 1A illustrates anumber of elements that are omitted from subsequent drawings for ease ofillustration, but may be included in any of the microelectronicassemblies disclosed herein. Examples of such elements include the die114, the FLI 138, the SLI 137, and/or the circuit board 134. Many of theelements of the microelectronic assembly 100A of FIG. 1A are included inother ones of the accompanying figures; the discussion of these elementsis not repeated when discussing these figures, and any of these elementsmay take any of the forms disclosed herein. A number of elements are notillustrated in FIG. 1A, but may be present in microelectronicsubassemblies disclosed herein; for example, additional activecomponents, such as additional dies, or additional passive components,such as surface-mount resistors, capacitors, and/or inductors, may bedisposed on the top surface or the bottom surface of the packagesubstrate 102, or embedded in the package substrate 102, and may beelectrically connected by the conductive pathways in the packagesubstrate 102.

FIG. 1B is a cross-sectional, magnified view of a portion of themicroelectronic assembly of FIG. 1A, as indicated by the dotted lines,in accordance with various embodiments. As shown in FIG. 1B, anx-dimension is length, a y-dimension is width, and a z-dimension isthickness. The microelectronic assembly 100B shows a package substrate102 with a conductive layer having a first conductive feature 118 with afirst thickness (T1) and a second conductive feature 128 with a secondthickness (T2), where T1 is different from T2. For example, as shown inFIG. 1A, T1 may be greater than T2. In some embodiments, T1 may be twiceT2. In some embodiments, T1 may be greater than twice T2. In someembodiments, T1 may be less than twice T2. The first and secondconductive features 118, 128 may have any suitable dimensions. In someembodiments, T1 may be between 4 micron (um) and 143 um. In someembodiments, T1 may be between 4 um and 40 um. In some embodiments, T1may be between 25 um and 100 um. In some embodiments, T1 may be between80 um and 143 um. In some embodiments, T2 may be between 2 um and 141um. In some embodiments, T2 may be between 2 um and 35 um. In someembodiments, T2 may be between 30 um and 95 um. In some embodiments, T2may be between 75 um and 141 um.

In some embodiments, the first and second conductive features 118, 128may have a non-rectangular cross-section, such that the first and secondconductive features 118, 128 have a non-uniform width (e.g.,y-dimension) along a thickness (e.g., z-dimension or z-height). Forexample, the side surfaces may taper or slant such that there is adifferential between a top width and a bottom width of the conductivefeature. For example, the first conductive feature 118 may have a firstwidth W1 on a bottom surface 171-1 and a second width W2 on a topsurface 171-2 and the second conductive feature 128 may have a firstwidth W3 on the bottom surface 171-1 and a second width W4 on the topsurface 171-2, where the first width (e.g., W1, W3) is less than thesecond width (e.g., W2, W4). In some embodiments, the first width (e.g.,W1, W3) may be between 2 um and 500 um. In some embodiments, the secondwidth (e.g., W2, W4) may be between 2 um and 500 um. In someembodiments, first and second conductive features 118, 128 may have alength (e.g., y-dimension, not shown) between 5 um and 5000 um.

As used herein, non-rectangular refers to a feature having surfaces thatdo not meet at right angles (e.g., not 90 degrees). For example, afeature may have linear top, bottom, and side surfaces, where the sidesurfaces (e.g., sides or sidewalls) meet the top and bottom surfaces atgreater than 90 degrees or less than 90 degrees. As used herein, afeature having “a non-uniform width,” “angled sidewalls,” “slopedsidewalls,” or “a non-rectilinear or non-rectangular cross-section”generally refers to a feature having sloped surfaces, where the sidesurfaces are non-perpendicular to a top surface and a bottom surface. Insome embodiments, the first and second conductive features may be firstand second traces, respectively. In some embodiments, a first trace mayhave a first thickness that is greater than a second thickness arrangedto carry a first signal having a first frequency, and a second trace mayhave a second thickness that is less than the first thickness and may bearranged to carry a second signal having a second frequency, where thesecond frequency is different from the first frequency. In someembodiments, the first and second frequencies may be between 100kilohertz (kHz) and 100 gigahertz (GHz). In some embodiments, the firstand/or second conductive feature may be a contact pad or may be a plane.

The package substrate 102 may also include the electrolesscatalyst-doped PID material 103 where the PID material 103 may havedifferent thicknesses relative to the different conductive featurethicknesses. For example, the PID material 103 may have a thirdthickness (T3) under the first conductive feature 118, a fourththickness (T4) under the second conductive feature 128, and a fifththickness (T5) which is measured from a bottom surface 171-1 of the PIDmaterial 103 to a top surface 171-2 of the PID material 103. In someembodiments, T4 may be greater than T3. In some embodiments, T5 may bebetween 7 um and 150 um. In some embodiments, T5 may be between 7 um and50 um. In some embodiments, T5 may be between 50 um and 100 um. In someembodiments, T5 may be between 100 um and 150 um.

As used herein, the term “lower density” and “higher density” arerelative terms indicating that the conductive pathways (e.g., includingconductive lines and conductive vias) in a lower density medium arelarger and/or have a greater pitch than the conductive pathways in ahigher density medium. For example, a higher density medium (e.g., thedie 114) may have a line or space pitch of approximately 10 microns,while a lower density medium (e.g., the package substrate 102) may havea line or space pitch of approximately 40-50 microns. In anotherexample, a higher density medium may have a line or space pitch of lessthan 20 microns, while a lower density medium may have a line or spacepitch greater than 40 microns. A higher density medium may bemanufactured using a modified semi-additive process or a semi-additivebuild-up process with advanced lithography (with small verticalinterconnect features formed by advanced laser or lithographyprocesses), while a lower density medium may be a printed circuit board(PCB) (e.g., circuit board 134) manufactured using a standard PCBprocess (e.g., a standard subtractive process using etch chemistry toremove areas of unwanted copper, and with coarse vertical interconnectfeatures formed by a standard laser process).

Although FIG. 1B shows only two conductive features 118, 128 havingparticular thicknesses (e.g., T1, T2), a microelectronic assembly mayinclude any number of conductive features, including more than twoconductive features, and the more than two conductive features may haveany suitable thicknesses including a thickness equal to T1 or T2, or athickness that is different from T1 or T2. Likewise, a microelectronicassembly may include any number of electroless catalyst-doped PID layershaving any suitable thickness, and the thickness of the electrolesscatalyst-doped PID layers may depend on the relative thicknesses of thetwo or more conductive features.

Any suitable techniques may be used to manufacture the microelectronicassemblies disclosed herein. For example, FIGS. 2A-2F are side,cross-sectional views of various stages in an example process formanufacturing a microelectronic assembly, in accordance with variousembodiments. Although the operations discussed below with FIGS. 2A-2F(and others of the accompanying drawings representing manufacturingprocesses) are illustrated in a particular order, these operations maybe performed in any suitable order. Additionally, although particularassemblies are illustrated in FIGS. 2A-2F (and others of theaccompanying drawings representing manufacturing processes), theoperations discussed below with reference to FIGS. 2A-2F may be used toform any suitable assemblies.

FIG. 2A illustrates an assembly 200A including a portion of a packagesubstrate 102 subsequent to depositing an electroless catalyst-doped PIDmaterial 203 on a top surface 272 of the portion of the packagesubstrate 102. The electroless catalyst-doped PID material 203 mayinclude any suitable photo-imageable dielectric material and anysuitable electroless catalyst, as described above with reference to FIG.1 . The electroless catalyst-doped PID material 203 may be formed usingany suitable technique, for example, lamination.

FIG. 2B illustrates an assembly 200B subsequent to patterning theelectroless catalyst-doped PID material 203 to provide a first opening253 for the formation of a larger conductive feature (e.g., conductivefeatures having a thickness greater than 150 um and/or a width greaterthan 500 um, such as a conductive via, a conductive pad, or a conductiveplane). The electroless catalyst-doped PID material 203 may be patternedusing any suitable technique, including a lithographic process (e.g.,exposing the electroless catalyst-doped PID material 203 to a radiationsource, for example, light). The first opening 253 may have any suitablesize and shape for forming a conductive feature having desiredcharacteristics. For example, the first opening 253 may be shaped toform a conductive via having a particular size and shape, such as arectangular cross-section.

FIG. 2C illustrates an assembly 200C subsequent to depositing a firstconductive material in the first opening 253 for the formation, or apartial formation, of a conductive via 119. In some embodiments, asshown in FIG. 2C, the first conductive material may be deposited topartially fill the first opening 253. In some embodiments, the firstconductive material may be deposited to fill the first opening 253. Thefirst conductive material may be deposited using any suitable technique,including, for example, electroplating, sputtering, or electrolessplating. The conductive via 119 may be formed from any suitableconductive material, for example, copper (Cu), aluminum (Al), gold (Au),silver (Ag), and/or alloys thereof. In some embodiments, a seed layer(not shown) may be deposited prior to depositing the first conductivematerial. In some embodiments, the seed layer may be omitted.

FIG. 2D illustrates an assembly 200D subsequent to laser drilling theelectroless catalyst-doped PID material 203 to form a second opening 255and a third opening 257. The second and third openings 255, 257 may beformed using any suitable technique, including, for example, laserdrilling, to selectively activate the electroless catalyst-doped PIDmaterial 203 and form openings having different thicknesses (e.g., T1and T2 as shown in FIG. 1 ). Any residue remaining in the second andthird openings 255, 257 may be cleaned away using any suitable process,such as a wet desmear process. In some embodiments, after laserablation, a portion (e.g., surfaces 245, 247 of the second and thirdopenings) of the electroless catalyst-doped PID material 203 may becatalytically activated and chemically different from portions of theelectroless catalyst-doped PID material 203 that were not exposed tolaser ablation.

FIG. 2E illustrates an assembly 200E subsequent to depositing a secondconductive material in the first opening 253, if necessary, to formconductive feature 119, and in the second and third openings 255, 257 toform conductive features 118, 128. The second conductive material may bedeposited in the first opening 253 using any suitable technique,including, for example, electroplating, sputtering, or electrolessplating. The second conductive material may be deposited in the secondand third openings 255, 257 using any suitable technique, for example,electroless plating. The second conductive material may be any suitableconductive material, including, copper, and may be a same conductivematerial as the first conductive material, or may be a differentconductive material. In some embodiments, exposed top surfaces 273 ofthe conductive features 118 and/or 128 may be planarized or polished toremove excess conductive material. In some embodiments, the top surfaces273 of the conductive material may be recessed to a desired thickness(e.g., T1, T2, T5) with a flash etching process, a wet etch or a dryetch process. In some embodiments, the conductive material may beremoved using a chemical mechanical planarization (CMP) process.

FIG. 2F illustrates an assembly 200F subsequent to forming additionalbuild-up layers 205 in the package substrate 102 (e.g., a dielectriclayer 260 having conductive pathways 261 over the top surfaces 273 ofthe conductive features 118, 128, 119). Additional layers may be builtup in the package substrate 102 by any suitable process, which is knownin the art, including a semi-additive process (SAP). For example,additional layers may be built up by depositing a dielectric material,forming openings in the dielectric material, and depositing conductivematerial in the openings to form conductive pathways. The openings maybe formed using any suitable technique, including, for example, laserdrilling. Any residue remaining in the opening may be cleaned away usingany suitable process, such as a wet desmear process. The conductivematerial may be deposited using any suitable technique, including, forexample, electroplating, sputtering, or electroless plating. Theconductive material may be any suitable conductive material, including,copper, and may be a same conductive material as the conductive features118, 128, or may be a different conductive material from the conductivefeatures 118, 128. The finished substrate may be a single packagesubstrate or may be a repeating unit that may undergo a singulationprocess in which each unit is separated from one another to create asingle package substrate. Further operations may be performed assuitable (e.g., attaching dies to the package substrate, attachingsolder balls for coupling to a circuit board, etc.).

Although FIG. 2 shows a particular number and arrangement of conductivefeatures 118, 128, 119 in a single electroless catalyst-doped PIDmaterial 203, these are simply exemplary and a package substrate mayhave any suitable number of electroless catalyst-doped PID layers havingany suitable number and arrangement of conductive features withdifferent thicknesses. Additional electroless catalyst-doped PID layershaving conductive features with different thicknesses may be formed byrepeating the process as described with respect to FIGS. 2A-2E.

FIG. 3 is a process flow diagram of an example method of forming amicroelectronic assembly including an electroless catalyst-doped PIDmaterial with a plurality of conductive structures having differentthicknesses, in accordance with various embodiments. At 302, deposit anelectroless catalyst-doped PID on a substrate. At 304, laser drill afirst opening having a first thickness and a second opening having asecond thickness in the electroless catalyst-doped PID, where the firstthickness is different than the second thickness. At 306, deposit aconductive material in the first and second openings to form a firstconductive structure having the first thickness and a second conductivestructure having the second thickness. The conductive material, such ascopper, may be deposited by, for example, electroless plating.

At 308, optionally, continue building up the substrate by addingadditional conductive and dielectric layers using any suitable process.Additional electroless catalyst-doped PID layers including conductivestructures having different thicknesses may be formed by repeating theprocess as described in 302 through 306. The finished substrate may be asingle package substrate or may be a repeating unit that may undergo asingulation process in which each unit is separated from one another tocreate a single package substrate.

FIG. 4 is a side, cross-sectional view of a microelectronic assembly100, in accordance with various embodiments. The microelectronicassembly 100 may include a package substrate 102 coupled to a circuitboard 134 on a first surface 470-1 and coupled to a die 114 on a secondsurface 470-2. The package substrate 102 may include a plurality ofdielectric layers having an electroless catalyst-doped PID material 403and a plurality of dielectric layers 405 that do not have theelectroless catalyst-doped PID material. The dielectric layers 403, 405may include conductive pathways for routing signals and power throughthe package substrate. The electroless catalyst-doped PID material 403may be formed as described above with reference to FIG. 2 . As shown inFIG. 4 , the package substrate 102 may include three electrolesscatalyst-doped PID material layers 403-1, 403-2, 403-3 and twodielectric layers 405-1, 405-2. The three electroless catalyst-doped PIDmaterial layers 403-1, 403-2, 403-3 may include a plurality ofconductive structures 418, 428, 419 having different thicknesses. Inparticular, the first electroless catalyst-doped PID material layer403-1 may include three conductive structures 418-1, 428-1, 419-1 havingthree different thicknesses, the second electroless catalyst-doped PIDmaterial layer 403-2 may include three conductive structures 418-2,428-2, 419-2 having three different thicknesses, and the thirdelectroless catalyst-doped PID material layer 403-2 may include twoconductive structures 418-3, 428-3 having different thicknesses. Thethird electroless catalyst-doped PID material layer 403-3 may furtherinclude a solder ball 438 for coupling to the die 114. The opening forthe solder ball 438 may be formed using any suitable technique,including a lithographical process.

The microelectronic assemblies disclosed herein may be used for anysuitable application. For example, in some embodiments, amicroelectronic assembly may include a die that may be used to providean ultra-high density and high bandwidth interconnect for fieldprogrammable gate array (FPGA) transceivers and III-V amplifiers. In anexample, a microelectronic assembly may include a die that may be aprocessing device (e.g., a CPU, a radio frequency chip, a powerconverter, a network processor, a GPU, a FPGA, a modem, an applicationsprocessor, etc.), and the die may include high bandwidth memory,transceiver circuitry, and/or input/output circuitry (e.g., Double DataRate transfer circuitry, Peripheral Component Interconnect Expresscircuitry, etc.).

In another example, a microelectronic assembly may include a die thatmay be a cache memory (e.g., a third-level cache memory), and one ormore dies that may be processing devices (e.g., a CPU, a radio frequencychip, a power converter, a network processor, a GPU, a FPGA, a modem, anapplications processor, etc.) that share the cache memory of the die.

The microelectronic assemblies disclosed herein may be included in anysuitable electronic component. FIG. 5 is a block diagram of an exampleelectrical device 1000 that may include one or more of themicroelectronic assemblies disclosed herein. For example, any suitableones of the components of the electrical device 1000 may be arranged inany of the microelectronic assemblies disclosed herein. A number ofcomponents are illustrated in FIG. 5 as included in the electricaldevice 1000, but any one or more of these components may be omitted orduplicated, as suitable for the application. In some embodiments, someor all of the components included in the electrical device 1000 may beattached to one or more motherboards. In some embodiments, some or allof these components are fabricated onto a single system-on-a-chip (SoC)die.

Additionally, in various embodiments, the electrical device 1000 may notinclude one or more of the components illustrated in FIG. 5 , but theelectrical device 1000 may include interface circuitry for coupling tothe one or more components. For example, the electrical device 1000 maynot include a display device 1006, but may include display deviceinterface circuitry (e.g., a connector and driver circuitry) to which adisplay device 1006 may be coupled. In another set of examples, theelectrical device 1000 may not include an audio input device 1024 or anaudio output device 1008, but may include audio input or output deviceinterface circuitry (e.g., connectors and supporting circuitry) to whichan audio input device 1024 or audio output device 1008 may be coupled.

The electrical device 1000 may include a processing device 1002 (e.g.,one or more processing devices). As used herein, the term “processingdevice” or “processor” may refer to any device or portion of a devicethat processes electronic data from registers and/or memory to transformthat electronic data into other electronic data that may be stored inregisters and/or memory. The processing device 1002 may include one ormore digital signal processors (DSPs), ASICs, CPUs, GPUs,cryptoprocessors (specialized processors that execute cryptographicalgorithms within hardware), server processors, or any other suitableprocessing devices. The electrical device 1000 may include a memory1004, which may itself include one or more memory devices such asvolatile memory (e.g., dynamic random access memory (DRAM)), nonvolatilememory (e.g., read-only memory (ROM)), flash memory, solid state memory,and/or a hard drive. In some embodiments, the memory 1004 may includememory that shares a die with the processing device 1002. This memorymay be used as cache memory and may include embedded dynamic randomaccess memory (eDRAM) or spin transfer torque magnetic random accessmemory (STT-M RAM).

In some embodiments, the electrical device 1000 may include acommunication chip 1012 (e.g., one or more communication chips). Forexample, the communication chip 1012 may be configured for managingwireless communications for the transfer of data to and from theelectrical device 1000. The term “wireless” and its derivatives may beused to describe circuits, devices, systems, methods, techniques,communications channels, etc., that may communicate data through the useof modulated electromagnetic radiation through a nonsolid medium. Theterm does not imply that the associated devices do not contain anywires, although in some embodiments they might not.

The communication chip 1012 may implement any of a number of wirelessstandards or protocols, including but not limited to Institute ofElectrical and Electronic Engineers (IEEE) standards including Wi-Fi(IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005Amendment), 3rd Generation Partnership Project (3GPP) Long-TermEvolution (LTE), 5G, 5G New Radio, along with any amendments, updates,and/or revisions (e.g., advanced LTE project, ultra-mobile broadband(UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16compatible Broadband Wireless Access (BWA) networks are generallyreferred to as WiMAX networks, an acronym that stands for WorldwideInteroperability for Microwave Access, which is a certification mark forproducts that pass conformity and interoperability tests for the IEEE802.16 standards. The communication chip 1012 may operate in accordancewith a Global System for Mobile Communication (GSM), General PacketRadio Service (GPRS), Universal Mobile Telecommunications System (UMTS),High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.The communication chip 1012 may operate in accordance with Enhanced Datafor GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN),Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN(E-UTRAN). The communication chip 1012 may operate in accordance withCode Division Multiple Access (CDMA), Time Division Multiple Access(TDMA), Digital Enhanced Cordless Telecommunications (DECT),Evolution-Data Optimized (EV-DO), and derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The communication chip 1012 may operate in accordance with otherwireless protocols in other embodiments. The electrical device 1000 mayinclude an antenna 1022 to facilitate wireless communications and/or toreceive other wireless communications (such as AM or FM radiotransmissions).

In some embodiments, the communication chip 1012 may manage wiredcommunications, such as electrical, optical, or any other suitablecommunication protocols (e.g., the Ethernet). As noted above, thecommunication chip 1012 may include multiple communication chips. Forinstance, a first communication chip 1012 may be dedicated toshorter-range wireless communications such as Wi-Fi or Bluetooth, and asecond communication chip 1012 may be dedicated to longer-range wirelesscommunications such as global positioning system (GPS), EDGE, GPRS,CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a firstcommunication chip 1012 may be dedicated to wireless communications, anda second communication chip 1012 may be dedicated to wiredcommunications.

The electrical device 1000 may include battery/power circuitry 1014. Thebattery/power circuitry 1014 may include one or more energy storagedevices (e.g., batteries or capacitors) and/or circuitry for couplingcomponents of the electrical device 1000 to an energy source separatefrom the electrical device 1000 (e.g., AC line power).

The electrical device 1000 may include a display device 1006 (orcorresponding interface circuitry, as discussed above). The displaydevice 1006 may include any visual indicators, such as a heads-updisplay, a computer monitor, a projector, a touchscreen display, aliquid crystal display (LCD), a light-emitting diode display, or a flatpanel display.

The electrical device 1000 may include an audio output device 1008 (orcorresponding interface circuitry, as discussed above). The audio outputdevice 1008 may include any device that generates an audible indicator,such as speakers, headsets, or earbuds.

The electrical device 1000 may include an audio input device 1024 (orcorresponding interface circuitry, as discussed above). The audio inputdevice 1024 may include any device that generates a signalrepresentative of a sound, such as microphones, microphone arrays, ordigital instruments (e.g., instruments having a musical instrumentdigital interface (MIDI) output).

The electrical device 1000 may include a GPS device 1018 (orcorresponding interface circuitry, as discussed above). The GPS device1018 may be in communication with a satellite-based system and mayreceive a location of the electrical device 1000, as known in the art.

The electrical device 1000 may include another output device 1010 (orcorresponding interface circuitry, as discussed above). Examples of theother output device 1010 may include an audio codec, a video codec, aprinter, a wired or wireless transmitter for providing information toother devices, or an additional storage device.

The electrical device 1000 may include another input device 1020 (orcorresponding interface circuitry, as discussed above). Examples of theother input device 1020 may include an accelerometer, a gyroscope, acompass, an image capture device, a keyboard, a cursor control devicesuch as a mouse, a stylus, a touchpad, a bar code reader, a QuickResponse (QR) code reader, any sensor, or a radio frequencyidentification (RFID) reader.

The electrical device 1000 may have any desired form factor, such as aportable, hand-held, or mobile electrical device (e.g., a cell phone, asmart phone, a mobile internet device, a music player, a tabletcomputer, a laptop computer, a netbook computer, an ultrabook computer,a personal digital assistant (PDA), an ultra-mobile personal computer,etc.), a desktop electrical device, a server or other networkedcomputing component, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a vehicle control unit, a digital camera, adigital video recorder, or a wearable electrical device. In someembodiments, the electrical device 1000 may be any other electronicdevice that processes data.

The following paragraphs provide various examples of the embodimentsdisclosed herein.

Example 1 is a microelectronic assembly, including a substrate layerhaving a surface, wherein the substrate layer includes a photo-imageabledielectric (PID) and an electroless catalyst, wherein the electrolesscatalyst includes one or more of palladium, gold, silver, ruthenium,cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum;a first conductive trace having a first thickness on the surface of thesubstrate layer; and a second conductive trace having a second thicknesson the surface of the substrate layer, wherein the first thickness isgreater than the second thickness.

Example 2 may include the subject matter of Example 1, and may furtherspecify that the electroless catalyst in the PID has a weight percent ofup to 10.

Example 3 may include the subject matter of Example 1, and may furtherspecify that the electroless catalyst in the PID is palladium having aweight percent of up to 5.

Example 4 may include the subject matter of Example 1, and may furtherspecify that the first thickness is between 4 um and 143 um.

Example 5 may include the subject matter of Example 1, and may furtherspecify that the second thickness is between 2 um and 141 um.

Example 6 may include the subject matter of Example 1, and may furtherspecify that the first and second conductive traces have slopedsidewalls.

Example 7 may include the subject matter of Example 1, and may furtherspecify that the substrate layer is in an interposer.

Example 8 is a microelectronic assembly, including a first conductivefeature having a first thickness in a layer of a package substrate,wherein the layer of the package substrate includes a photo-imageabledielectric (PID); and a second conductive feature having a secondthickness in the layer of the package substrate, wherein the secondthickness is different from the first thickness, and wherein the firstand second conductive features have sloped sidewalls.

Example 9 may include the subject matter of Example 8, and may furtherspecify that the PID includes one or more of palladium, gold, silver,ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, ortantalum.

Example 10 may include the subject matter of Example 8, and may furtherspecify that the first and second conductive features are traces.

Example 11 may include the subject matter of Example 8, and may furtherspecify that the first and second conductive features are contact pads.

Example 12 may include the subject matter of Example 8, and may furtherspecify that the first and second conductive features are planes.

Example 13 may include the subject matter of Example 8, and may furtherspecify that the first thickness is between 4 um and 143 um.

Example 14 may include the subject matter of Example 8, and may furtherspecify that the second thickness is between 2 um and 141 um.

Example 15 may include the subject matter of Example 8, and may furtherinclude a die electrically coupled to the package substrate.

Example 16 may include the subject matter of Example 15, and may furtherspecify that the die is a central processing unit, a radio frequencychip, a power converter, or a network processor.

Example 17 may include the subject matter of Example 15, and may furtherspecify that the first conductive feature or the second conductivefeature is electrically coupled to the die via conductive pathways inthe package substrate.

Example 18 is a computing device, including a package substrate having afirst surface and an opposing second surface, the package substrateincluding a layer including a photo-imageable dielectric (PID); a firstconductive trace having a first thickness in the layer of the packagesubstrate; and a second conductive trace having a second thickness inthe layer of the package substrate, wherein the second thickness isdifferent from the first thickness, and wherein the first and secondconductive traces have sloped sidewalls; a circuit board coupled to thefirst surface of the package substrate; and a die coupled to the secondsurface of the package substrate.

Example 19 may include the subject matter of Example 18, and may furtherspecify that the first thickness is between 4 um and 143 um.

Example 20 may include the subject matter of Example 18, and may furtherspecify that the second thickness is between 2 um and 141 um.

Example 21 may include the subject matter of Example 18, and may furtherspecify that the PID includes one or more of palladium, gold, silver,ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, ortantalum.

Example 22 may include the subject matter of any of Examples 18-21, andmay further specify that the computing device is a server device.

Example 23 may include the subject matter of any of Examples 18-21, andmay further specify that the computing device is a portable computingdevice.

Example 24 may include the subject matter of any of Examples 18-21, andmay further specify that the computing device is a wearable computingdevice.

Example 25 is a method of manufacturing a microelectronic assembly,including depositing an electroless catalyst-doped photo-imageabledielectric (PID) on a substrate; laser drilling the electrolesscatalyst-doped PID to form a first opening having a first thickness anda second opening having a second thickness, wherein the first thicknessis greater than the second thickness; and depositing a conductivematerial in the first opening to form a first conductive trace havingthe first thickness and in the second opening to form a secondconductive trace having the second thickness.

Example 26 may include the subject matter of Example 25, and may furtherspecify that the first thickness is between 4 um and 143 um.

Example 27 may include the subject matter of Example 25, and may furtherspecify that the second thickness is between 2 um and 141 um.

Example 28 may include the subject matter of Example 25, and may furtherspecify that a thickness of the electroless catalyst-doped PID isbetween 7 um and 150 um.

Example 29 may include the subject matter of Example 25, and may furtherspecify that the conductive material is deposited using an electrolessplating process.

Example 30 may include the subject matter of Example 25, and may furtherinclude removing a portion of the conductive material.

Example 31 may include the subject matter of Example 30, and may furtherspecify that the portion of the conductive material is removed using achemical mechanical planarization process.

Example 32 may include the subject matter of Example 25, and may furtherinclude forming a dielectric layer on the electroless catalyst-doped PIDincluding the first and second conductive traces.

Example 33 may include the subject matter of Example 25, and may furtherspecify that the conductive material is a second conductive material,and may further include lithographically developing, prior to laserdrilling, the electroless catalyst-doped PID to form a third opening;and depositing a first conductive material in the third opening to forma conductive feature.

Example 34 may include the subject matter of Example 33, and may furtherspecify that the first conductive material is deposited using anelectrolytic process.

Example 35 may include the subject matter of Example 25, and may furtherspecify that the electroless catalyst in the PID has a weight percent ofup to 10.

Example 36 may include the subject matter of Example 25, and may furtherspecify that the electroless catalyst-doped PID includesdiazobenzoquionone or acrylate.

1. A microelectronic assembly, comprising: a dielectric layer, in asubstrate, including an electroless catalyst, wherein the electrolesscatalyst includes one or more of palladium, gold, silver, ruthenium,cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum;a first conductive trace having a first thickness in the dielectriclayer, wherein the first thickness is between 4 um and 143 um; and asecond conductive trace having a second thickness in the dielectriclayer, wherein the second thickness is between 2 um and 141 um, whereinthe first thickness is greater than the second thickness, and whereinthe first conductive trace and the second conductive trace have slopedsidewalls.
 2. The microelectronic assembly of claim 1, wherein theelectroless catalyst in the dielectric layer has a weight percent of upto
 10. 3. The microelectronic assembly of claim 1, wherein theelectroless catalyst in the dielectric layer is palladium having aweight percent of up to
 5. 4. The microelectronic assembly of claim 1,wherein the dielectric layer is doped by the electroless catalyst. 5.The microelectronic assembly of claim 1, further comprising: a dieelectrically coupled to the substrate.
 6. The microelectronic assemblyof claim 5, wherein the die is a central processing unit, a radiofrequency chip, a power converter, or a network processor.
 7. Themicroelectronic assembly of claim 1, wherein the substrate is aninterposer.
 8. A microelectronic assembly, comprising: a firstconductive feature having a first thickness in a dielectric layer, of asubstrate, the dielectric layer including an electroless catalyst,wherein the first thickness is between 4 um and 143 um; and a secondconductive feature having a second thickness in the dielectric layer ofthe substrate, wherein the second thickness is between 2 um and 141 um,wherein the second thickness is different from the first thickness, andwherein the first and second conductive features have sloped sidewalls.9. The microelectronic assembly of claim 8, wherein the electrolesscatalyst includes one or more of palladium, gold, silver, ruthenium,cobalt, copper, nickel, titanium, aluminum, lead, silicon, or tantalum.10. The microelectronic assembly of claim 8, wherein the first andsecond conductive features are traces.
 11. The microelectronic assemblyof claim 8, wherein the dielectric layer is doped by the electrolesscatalyst.
 12. The microelectronic assembly of claim 8, furthercomprising: a die electrically coupled to the substrate.
 13. Themicroelectronic assembly of claim 12, wherein the die is a centralprocessing unit, a radio frequency chip, a power converter, or a networkprocessor.
 14. The microelectronic assembly of claim 12, wherein thefirst conductive feature or the second conductive feature iselectrically coupled to the die via conductive pathways in thesubstrate.
 15. A computing device, comprising: a package substratehaving a first surface and an opposing second surface, the packagesubstrate comprising: a dielectric layer including an electrolesscatalyst; a first conductive trace having a first thickness in thedielectric layer, wherein the first thickness is between 4 um and 143um; and a second conductive trace having a second thickness in thedielectric layer, wherein the second thickness is between 2 um and 141um, wherein the second thickness is different from the first thickness,and wherein the first conductive trace and the second conductive tracehave sloped sidewalls; a circuit board coupled to the first surface ofthe package substrate; and a die coupled to the second surface of thepackage substrate.
 16. The computing device of claim 15, wherein thedielectric layer is doped by the electroless catalyst.
 17. The computingdevice of claim 15, wherein the electroless catalyst includes one ormore of palladium, gold, silver, ruthenium, cobalt, copper, nickel,titanium, aluminum, lead, silicon, or tantalum.
 18. The computing deviceof claim 15, wherein the computing device is a server device.
 19. Thecomputing device of claim 15, wherein the computing device is a portablecomputing device.
 20. The computing device of claim 15, wherein thecomputing device is a wearable computing device.